Generally, data is stored as charge in an isolated cell capacitor. Because the capacitor cannot be perfect, the stored charge is leaked outside due to leakage current. Accordingly, before data fade out completely, the stored data should be amplified to be re-stored, which is called a refresh operation.
The refresh operation is evoked when an external command is received. In response to the external command, a word line corresponding to a row address is turned on and, in turn, activates a sense amplifier. During the refresh operation, there is no data input/output.
There are roughly two kinds of refresh operation schemes, a self refresh and an auto refresh. The entire memory cells are refreshed in response to one command input in the self refresh while respective refresh commands should be inputted every time in the auto refresh.
For reference, it will be described for timing of the refresh operation.
First, refresh time means time until the entire memory cells lost data, which is the period between one refresh on a particular memory cell and the next refresh. This is related to memory cell process or the size of the cell. Further, the number of RAS signals that are required to refresh the entthe number of RAS signals that is required for completely refresh the entire cells in a semiconductor memory device is called as a refresh cycle.
Next, it will be described for generation of an internal control signal for the refresh operation with a row path controlling circuit of the semiconductor memory device.
FIG. 1 provides a block diagram of a semiconductor memory device having a row path control circuit in prior art.
Referring to FIG. 1, the semiconductor memory device in prior art comprises an input buffer/command decoding unit 10 for receiving external commands CLK, CKE, /RAS, /CAS, /WE to generate operating signals REF, ACT, RD, WT, BAj, an internal address counting unit 11 for receiving the refresh signal REF to generate an internal address IAX<0˜i>, a row address latching unit 12 for outputting a row address AX<0˜i> under control of an active command ACT_COM and the refresh signal REF, a column address latching unit 13 for outputting a column address AY<0˜i> under control of the read signal RD and the write signal WT, a row pre-decoding unit 14 for decoding a part of the row address AX<0˜i>, a column pre-decoding unit 15 for decoding a part of the column address AY<0˜i>, a row decoding unit 18 for activating a word line WL by the output signal of the row pre-decoding unit 14, a column decoding unit 21 for decoding the output signal of the column pre-decoding unit 15 to select a column line, a row controlling unit 16 for receiving the bank signal Bai of the input buffer/command decoding unit 10 to generate a sense amplifier enable signal SAEN, an SA controlling unit 17 for controlling a sense amplifier block 19 under control of the sense amplifier enable signal SAEN, a memory array block 20 having a number of unit memory cells, and the sense amplifier block 19 for sensing and amplifying the memory cell data of the word line that is selected by the SA controlling unit 17.
FIG. 2 shows an internal circuit diagram of the row address latching unit 12 in FIG. 1.
Referring to FIG. 2, the row address latching unit 12 includes an inner latching unit 25 for outputting the internal address IAX<0,i> as the row address AX<0˜i> in response to activation of the refresh signal REF, and an outer latching unit 26 for outputting the address A<0˜i> as the row address AX<0˜i> in response to activation of the external input active command ACT_COM.
In particular, the inner latching unit 25 includes an inverter I1 for inverting the refresh signal, a PMOS transistor PM1 having the output signal of the inverter I1 as its gate input, a PMOS transistor PM2 having the internal address IAX<0˜i> as its gate input, the PMOS transistors PM1, PM2 being serially coupled to each other between a power voltage VDD and an output node, an NMOS transistor NM1 having the internal address IAX<0˜i> as its gate input, and an NMOS transistor NM2 having the refresh signal REF as its gate input, the NMOS transistors NM1, NM2 being serially coupled to each other between the output node and a power voltage VSS.
The outer latching unit 26 includes an inverter I2 for inverting the active command ACT_COM, PMOS transistor PM3 having the output signal of the inverter I2 as its gate input, a PMOS transistor PM4 having the address A<0˜i> as its gate input, the PMOS transistors PM3, PM4 being serially coupled to each other between the power voltage VDD and the output node, an NMOS transistor NM3 having the address A<0˜i> as its gate input, and an NMOS transistor NM4 having the active command ACT_COM as its gate, the NMOS transistors NM3, NM4 being serially coupled to each other between the output node and the power voltage VSS.
FIG. 3 describes an internal circuit diagram of a bank driving signal generating unit in the input buffer/command decoding unit 10 in FIG. 1.
Referring to FIG. 3, the bank signal generating unit is formed with a cross-coupled NAND latch having the active signal ACT as a set signal and having a pre-charge signal PRE and a refresh pre-charge signal REBA as reset signals to generate the bank signal BAi.
Next, it will be described for the normal operation with active command input and the refresh operation with refresh command input in the operation of the semiconductor memory device having the row path controlling unit.
First, in the normal operation, the inputted active command ACT_COM is activated to the active signal ACT through the input buffer/command decoding unit 10. In turn, the address A<0˜i> that is inputted along with the external command is outputted as the row address AX<0˜i> through the row address latching unit 12 that is controlled by the active command ACT_COM and goes through the row pre-decoding unit 14 and the row decoding unit 18 to activate the corresponding word line WL. Further, the bank signal generating unit activates the bank signal Bai in response to the active signal ACT. In turn, the row controlling unit 16 activates the sense amplifier enable signal SAEN in response to activation of the bank signal Bai to make the sense amplifier enable signal SAEN be activated through the SA controlling unit 17 to sense and amplify the memory cell data. After that, the input buffer/command decoding unit 10 decodes the external commands CLK, CKE, /RAS, /CAS, /WE to activate the read signal RD or the write signal WT to control the column address latching unit 13 to output the inputted address A<0˜i> as the column address AY<0˜i>. The column address AY<0˜i> goes through the column pre-decoding unit 15 and the column decoding unit 21 to perform a read operation by selectively outputting data from the sense amplifier block 19 or perform a write operation by over-writing external data onto the sense amplifier block 19. The operation is finished when the pre-charge command PRE_COM is inputted.
Next, when the external commands CLK, CKE, /RAS, /CAS, /WE are inputted, the refresh signal is activated by the input buffer/command decoding unit 10. In turn, the inner address counting unit 11 generates the internal address IAX<0˜i> under control of the refresh signal REF. The internal address IAX<0˜i> is outputted as the row address AX<0˜i> through the row address latching unit 12 that is controlled by the refresh signal REF, to go through the row pre-decoding unit 14 and the row decoding unit 18 to activate the corresponding word line WL. Further, the bank signal generating unit activates the bank signal Bai in response to the active signal ACT. In turn, the row controlling unit 16 activates the sense amplifier enable signal SAEN in response to activation of the bank signal Bai to make the sense amplifier block 19 activated by the SA controlling unit 17 to sense and amplify the memory cell data in the selected word line WL. The memory cell data that is amplified by the sense amplifier block 19 is stored at the memory array block 20 and, then, the refresh operation is finished in response to activation of the refresh pre-charge signal REBA.
FIG. 4 exemplifies a timing diagram of the normal operation of the block in FIG. 1.
Referring to FIG. 4, the inputted active command ACT_COM is activated to the active signal ACT and, simultaneously, the inputted address A(0) is activated to the row address AX(0). In turn, the bank signal Bai is activated in response to the active signal ACT and the word line WL0 and the sense amplifier enable signal SAEN of the corresponding bank are activated. In turn, in response to the input of the pre-charge command PRE_COM, the bank signal Bai, the word line WL0 and the sense amplifier enable signal SAEN are deactivated.
After that, when the active command and address A(m) are inputted, another normal operation for the word line WLm begins.
FIG. 5 represents a timing diagram of the refresh operation of the block in FIG. 1.
Referring to FIG. 5, in response to input of an auto-refresh command Auto Refresh_COM, the refresh signal REF is activated. The internal address IAX(0) is generated in response to activation of the refresh signal REF and activated to the row address AX(0). The bank signal Bai is activated by the active signal ACT that is activated in response to the refresh signal REF so as to activate the corresponding word line WL0 and the sense amplifier enable signal SAEN. In turn, the bank signal Bai is deactivated to deactivate the refresh signal REF, the word line WL0 and the sense amplifier enable signal SAEN.
After that, the auto-refresh command AutoRefresh_COM is inputted again, the sequential internal address IAX(1) is generated to refresh the next word line WL1 in the bank.
For the reference, the period between the input of the active command and the input of the next active command is called as RAS cycle tRC and the minimum period by which the auto-refresh command can be inputted is called as tRCmin. FIGS. 4 and 5 show the activation of the internal control signals for one period of tRC after the active command and the address are inputted.
On the hand, Table 1 is provided to compare the refresh operation of a 256 Mb/512 Mb memory device to a 1 Gb memory device in JEDEC(Jointed Electron Device Engineering Council) specification.
TABLE 1Density256 Mb/512 Mb1 GbRow Add.A0–A12A0–A13# of Row8192 ea16384 eaTRFC (min)72 ns @DDR333120 nstREFI7.8 us7.8 usRefresh Cycle8 K/64 ms8 K/64 ms# of Active WL1 ea @tRFC (min)2 ea @tRFC (min)per Bank
Referring to Table 1, the 256 Mb/512 Mb memory device has 8192 word lines with 13 row addresses A0–A12 while the 1 Gb memory device has 16384 word lines with 14 row addresses A0–A13. On the other hand, both of the 256 Mb/512 Mb memory device and the 1 Gb memory device have the same refresh cycle specification 8 K/64 ms. Because the 1 Gb memory device has 16 K word lines per bank, it should activate two times of word lines during the same tRFC compared to the 256 Mb/512 Mb memory device to follow the specification for performing 8K times refresh operations during 64 ms.
Accordingly, while 1 word line per bank is activated in the refresh operation in prior art, the 1 Gb memory device should activates two times of the word lines, which has relative weakness to peak current.
Further, because the tRFCmin=72 ns of the 256 Mb/512 Mb memory device is different from the tRFCmin=120 ns of the 1 Gb memory device, two memory devices cannot be used in a system that does not support both of the tRFCmin.